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You mean, your code operates it this way?
That's how I2C works. Bus drivers should operate as open drain, which is simple with a FPGA I/O pin.
DE2 is a Terasic product, shipped with Verilog
demonstration code. It's basically working, but not particularly instructive. The I2C related code, as far as I'm aware of is pretty basic and can be converted to VHDL without deep Verilog knowledge (in my opinion). Others have probably written own I2C code from the scratch based on the NXP specification or used IP from the internet.
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No. It seems it has a delay that makes the sda to go from 'H' to 'L' in this way. My code is made from scratch ,and when i make simulations in modelsim it works, but when i implement on the bord, it acts like this.
What is NXP specification? I never heard about this. Thank you!
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