i2c problem

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The Sda line changes the state on the scl='1'

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You mean, your code operates it this way?

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The sda is pulled up to vdd.

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That's how I2C works. Bus drivers should operate as open drain, which is simple with a FPGA I/O pin.

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Does altera provide any solutions for these problems?

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DE2 is a Terasic product, shipped with Verilog demonstration code. It's basically working, but not particularly instructive. The I2C related code, as far as I'm aware of is pretty basic and can be converted to VHDL without deep Verilog knowledge (in my opinion). Others have probably written own I2C code from the scratch based on the NXP specification or used IP from the internet.