I want to know the max speed of NIOS ii based on cyclone iii EP3C120N780C

Thank you very much,BadOmen! The NIOS II/f is now working on the 166.7mhz system clock.I just constraining the input clock,altpll and seg7led I/O port obey your suggestion.But the TimeQuest still report mass unconstrained paths:

--1)Setup Analysis:

Unconstrained Input Ports:(1)altera_reserved_tms:No input delay, min/max delays, or false-path exceptions found; (2)altera_reserved_tdi:No input delay, min/max delays, or false-path exceptions found.

totally 63 unconstrained paths.

Unconstrained Output Ports:(1)altera_reserved_tdo:No output delay, min/max delays, or false-path exceptions found.

totally 1 unconstrained paths.

--2)Hold Analysis:

The unconstrained paths are the same as above.

I wonder at the NIOS II/f is working under so many unconstrained paths.

How to clear these unconstrained paths?

What's the altera_reserved_tms,_tdi,_tdo meaning?

Thank for your suggestion.The clock and I/O constraint is now correct.But my sopc system still have 63 unconstrained path.

In order to test the highest speed of NIOS II based on EP3C120N780C7,I construct a simplest sopc system which only using a NIOS II/f CPU,ALTPLL(50mhz in,100mhz,166.7mhz,2.5khz(seg7led clk) out),Timer,JTAG,ON-Chip RAM and a seg7led driver IP for display the status of the C program running.

The NIOS II C program is normal at 100mhz system clk,but always dead when the sytem clk exceed 100mhz(125mhz,150mhz,166mhz).

The uncontrained path is the only limit to the speed?

The SOPC builder automatically generates a .sdc constraints file,I build another .sdc file for clk and I/O,all this .sdc file was add to the project,But the TimeQuest analysis still report 63 unconstrained path,I don't know how to resolve these path .

(from)altera_reserved_tdi (to)asopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[0] altera_reserved_tck

altera_reserved_tdi asopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[15] altera_reserved_tck

altera_reserved_tdi asopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[35] altera_reserved_tck

altera_reserved_tdi asopc:inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module_tck:the_cpu_0_jtag_debug_module_tck|sr[37] altera_reserved_tck

altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9] altera_reserved_tck

altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|state altera_reserved_tck

altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[0] altera_reserved_tck

altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[10] altera_reserved_tck

altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[0] altera_reserved_tck

altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[7] altera_reserved_tck

altera_reserved_tdi asopc:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|write_stalled altera_reserved_tck

altera_reserved_tdi sld_hub:sld_hub_inst|irsr_reg[6] altera_reserved_tck

altera_reserved_tdi sld_hub:sld_hub_inst|jtag_ir_reg[9] altera_reserved_tck

altera_reserved_tdi sld_hub:sld_hub_inst|node_ena[1]~reg0 altera_reserved_tck

altera_reserved_tdi sld_hub:sld_hub_inst|node_ena[2]~reg0 altera_reserved_tck

altera_reserved_tdi sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] altera_reserved_tck

altera_reserved_tdi sld_hub:sld_hub_inst|tdo_bypass_reg altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|hub_mode_reg[0] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|hub_mode_reg[1] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[1][0] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[1][1] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[1][2] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[1][3] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[1][4] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[2][0] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[2][1] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[2][2] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[2][3] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|irf_reg[2][4] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|node_ena[1]~reg0 altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|node_ena[2]~reg0 altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|reset_ena_reg altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[1][0] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[1][1] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[1][2] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[1][3] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[1][4] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[2][0] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[2][1] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[2][2] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[2][3] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|shadow_irf_reg[2][4] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|virtual_dr_scan_reg altera_reserved_tck

altera_reserved_tms sld_hub:sld_hub_inst|virtual_ir_scan_reg altera_reserved_tck

Nope they are based on board trace delays and the timing of the devices connected to the FPGA. The output delays are based on trace delay and the setup and hold times of the external device. The input delays are based on the trace delays and min/max clock to out times of the external device. Typically the datasheets will only define the maximum clock to out (Tco) and you can assume the minimum is 0.

What I'm describing are called "system centric" constraints. The FPGA data sheet approach that you are referring to is called "FPGA centric" constraints. Both work but I recommend the system constraint approach since it's less work and less error prone.

I forgot to mention these examples: http://www.altera.com/support/examples/timequest/exm-timequest.html

In order to constrain the I/Os,I must specify the max/min input and output delays.But how to decide the max/min value? Should I get it from the Electrical Characteristics in the CycloneIII Handbook?

Thank for BadOmen.

This design should get you started: http://www.altera.com/support/examples/nios2/exm-c2h-mandelbrot.html

It targets the Nios II kit which uses the same base board. If you search around on the Nios wiki you'll probably find a couple other designs that target the same base board with Timequest .sdc constraints.

When constraining the input and outputs you need to specify minimum and maximum delays which take off-chip trace delays and external IC timing constraints like Tsu, Th, and Tco into consideration. Some I/O may be slow and asynchronous to your system in which case you may be able to 'cut' those paths. Some I/O are also multi-cycle which you can set multi-cycle constraints for. If you do all of the above then you should end up with no un-constrained I/O.

Here are some other good docs to read:

http://www.altera.com/literature/hb/qts/qts_qii5v3_02.pdf

http://www.altera.com/literature/an/an433.pdf?gsa_pos=5&wt.oss_r=1&wt.oss=source%20synchronous

Thank you for reply.I'll study how to meeting the timing and constraining my design.After TimeQuest timing analyzer,I find some unconstrained paths:

Illegal Clocks 0 0

Unconstrained Clocks 1 1

Unconstrained Input Ports 3 3

Unconstrained Input Port Paths 67 67

Unconstrained Output Ports 13 13

Unconstrained Output Port Paths 13 13

I don't know how to add the constrain in the synthesis.

Are you meeting timing when you re-compile for a higher speed? Also are you constraining your design?

Reaching 167MHz is possible on Cyclone III but I wouldn't expect to get it running any faster than that. Instead of cranking the CPU clock speed up I would invest some time looking for bottlenecks and determining what exactly needs to run fast. Then you can optimize or offload algorithms into dedicated hardware. This should result in lower power, more processing efficiency, and typically more scaling (once you hit the limits of the silicon you can't turn up the clock speed anymore).