Honored Contributor
Honored ContributorThis design should get you started: http://www.altera.com/support/examples/nios2/exm-c2h-mandelbrot.html
It targets the Nios II kit which uses the same base board. If you search around on the Nios wiki you'll probably find a couple other designs that target the same base board with Timequest .sdc constraints. When constraining the input and outputs you need to specify minimum and maximum delays which take off-chip trace delays and external IC timing constraints like Tsu, Th, and Tco into consideration. Some I/O may be slow and asynchronous to your system in which case you may be able to 'cut' those paths. Some I/O are also multi-cycle which you can set multi-cycle constraints for. If you do all of the above then you should end up with no un-constrained I/O. Here are some other good docs to read: http://www.altera.com/literature/hb/qts/qts_qii5v3_02.pdf http://www.altera.com/literature/an/an433.pdf?gsa_pos=5&wt.oss_r=1&wt.oss=source%20synchronous
