I want to know the max speed of NIOS ii based on cyclone iii EP3C120N780C

Nope they are based on board trace delays and the timing of the devices connected to the FPGA. The output delays are based on trace delay and the setup and hold times of the external device. The input delays are based on the trace delays and min/max clock to out times of the external device. Typically the datasheets will only define the maximum clock to out (Tco) and you can assume the minimum is 0.

What I'm describing are called "system centric" constraints. The FPGA data sheet approach that you are referring to is called "FPGA centric" constraints. Both work but I recommend the system constraint approach since it's less work and less error prone.

I forgot to mention these examples: http://www.altera.com/support/examples/timequest/exm-timequest.html