Forum Discussion
Altera_Forum
Honored Contributor
16 years agoThank you for reply.I'll study how to meeting the timing and constraining my design.After TimeQuest timing analyzer,I find some unconstrained paths:
Illegal Clocks 0 0 Unconstrained Clocks 1 1 Unconstrained Input Ports 3 3 Unconstrained Input Port Paths 67 67 Unconstrained Output Ports 13 13 Unconstrained Output Port Paths 13 13 I don't know how to add the constrain in the synthesis.