Altera_Forum
Honored Contributor
11 years agoI am stuck
I tried to implement the following code, copied from Page 37 of the ALTERA Verilog manual:
module compinst (data,clock,clearn,presetn,a,b,c,gn,d,q_out,y,wn); input data,clock,clearn,presetn,a,b,c,gn; input [3:0]d; output q_out,y,wn; dff dff1 (.d (data),.q(q_out),.clk(clock),.clrn(clearn),.prn(presetn)); a_74151b mux (c,b,a,d,gn,y,wn); endmodule When I compile the code, I get the following error message: Error: Node instance "mux" instantiates undefined entity "a_74151b" Being a novice, I would appreciate explanation and correction of the error. I am using Quartus II. Andrew