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Altera_Forum
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12 years ago

I am stuck

I tried to implement the following code, copied from Page 37 of the ALTERA Verilog manual: module compinst (data,clock,clearn,presetn,a,b,c,gn,d,q_out,y,wn); input data,clock,clearn,presetn...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thanks Alex. One more question: where does one find a tutorial or some explanation on how to use the state diagram feature?

Andrew