how tooutput a high speed clock

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I need a clock to control high speed AD.But I measure it with oscillograph finding it is very bad so that AD can't work.

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What clock rate is your ADC?

The design documents here;

http://www.ovro.caltech.edu/~dwh/carma_board/

Discuss the design of a 1GHz ADC.

If you can provide more detail, I can offer suggestions.

Cheers,

Dave

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I need a clock to control high speed AD.But I measure it with oscillograph finding it is very bad so that AD can't work.

thank you very much

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Bad in what sense? Is it due to incompatible voltage levels (for example ADC is expecting clock in LVPECL standard and FPGA is outputting 3.3V LVCMOS) or due to high clock jitter?

Normally you would not want to clock high performance ADC from FPGA, because FPGA output clocks have relatively high jitter.

FPGA IO signals can't be good or bad as such. They undergo the general rules of interfacing high speed digital signals. As you are talking about 1 MHz clock frequency, I guess, the problem may be, that you aren't familar with logic signals in the FPGA typical speed range.

A good standard to get clean square waves is using source side impedance matching. Presumed you have a cable or PCB trace with e.g 50 to 80 ohm characteristic impedance, supplement the FPGA pins output impedance with a series resistor to make the sum match the characteristic impedance. The method will work with a low to moderate capacitive load.

For a detailed discussion, you should tell more about the problem you're facing. Posting waveform photos isn't a bad idea.

P.S.: For high performance requirements, e.g. to achieve low jitter, it may be reasonable, to send the clock signal using the LVDS IO standard and place a LVDS receiver near the load. This will effectively eliminate most common mode interferences possibly present in a highly populated digital circuit.

I'm just a beginner and not familar with FPGA.My problem is that I don't how to deal with the signal of FPGA including input and output. I used a comparator to deal with the clock from FPGA.Is there other solution to deal with it.

Thank you very much

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I need change the ADC clock to control sampling rate(we are designing a digital storage osciioscope). I just need a 1M time Sampling clock and 200M Equivalent Sampling,so I need a clock from FPGA. I just change the ADC clock's frenquency to get different sampling rate.

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If you are designing an oscilloscope, then the number of bits in your ADC, and the highest sampling frequency determine your required jitter. For example, if your ADC is 12-bits, and the maximum frequency is 100MHz, then the maximum jitter (clock plus ADC) is

tj < 1/(2*pi*fmax*2^B ) = 1/(2*pi*100MHz*2^12) = 0.39ps

Which is a difficult specification to meet. You would generally use an external clock source (low jitter crystal or VCO) to implement such a clock.

Why do you want to implement an equivalent sampling scheme at 200MHz? This is a low enough frequency that you can implement a real-time sampling oscilloscope. There's no advantage in trying to achieve equivalent time sampling at this frequency, as you still need to meet the analog input bandwidth and jitter specification of a real-time sampling scope.

Cheers,

Dave

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Because I just have low speed ADC,but I need sample a high frenquency signal.

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How do you know this ADC can sample a high-frequency signal? What is the analog input bandwidth of the ADC? Do you have a data sheet for the ADC? Please post a link.

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But if I use an external clock to control ADC,how can I change the sampling rate.

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You can use an external clock source that is programmable.

However, its not clear that you understand how equivalent sampling (also known as repetitive interlaced sampling) works either. How do you think you can use a 1MHz ADC to sample at 200MHz?

Cheers,

Dave

You can use an external clock source that is programmable.

An external clock source that is programmable? Can you give a example(the chip's name )?

As you know,I am designing an oscilloscope so the sample rate Varies greatly. I design divider that is programmable using FPGA to control ADC clock.

Equivalent sampling is to use low-frequency sampling high-frequency signals.

I use the sequential sampling technique. sampling a point a cycle of signal, and delay a slight time(slight delay determines the sampling rate ). I use the 200M counting clock signalto get signal's period. And I design a state machine get the clock to control AD.

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You can use an external clock source that is programmable.

An external clock source that is programmable? Can you give a example(the chip's name)?

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One option is to use a direct digital synthesizer (DDS). Analog devices has many devices.

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As you know,I am designing an oscilloscope so the sample rate Varies greatly.

I design divider that is programmable using FPGA to control ADC clock.

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The sample rate of the ADC does not have to vary at all. You can vary the sample rate once you have the data on the FPGA using multi-rate sampling and digital filtering. While this may seem more complex, it may in fact be simpler, in that your ADC operates at a fixed frequency. For example, I run my 1GHz ADCs at 1GHz all the time. Digital filters are then used to generate 250MHz, 125MHz, etc, down to 2MHz sampling modes.

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Equivalent sampling is to use low-frequency sampling high-frequency signals.

I use the sequential sampling technique. sampling a point a cycle of signal, and delay a slight time(slight delay determines the sampling rate ). I use the 200M counting clock signalto get signal's period. And I design a state machine get the clock to control AD.

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Ok, glad to hear you understand how to make this work. However, this scheme will not work with any old 1MHz ADC. The 1MHz ADC must have an input analog bandwidth in excess of 100MHz and the ADC clock plus aperture jitter must meet the requirements I state above, or you must have a wide bandwidth track-and-hold (T/H) or sample-and-hold (S/H) in front of your ADC, with in excess of 100MHz of bandwidth clocked by a clock with the jitter requirements I state above.

You cannot avoid the input bandwidth requirement, and having a very clean clock source.

Why are you trying to use a 1MHz ADC? Does it meet the requirements I have pointed out?

Cheers,

Dave