how tooutput a high speed clock

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I need a clock to control high speed AD.But I measure it with oscillograph finding it is very bad so that AD can't work.

thank you very much

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Bad in what sense? Is it due to incompatible voltage levels (for example ADC is expecting clock in LVPECL standard and FPGA is outputting 3.3V LVCMOS) or due to high clock jitter?

Normally you would not want to clock high performance ADC from FPGA, because FPGA output clocks have relatively high jitter.