how tooutput a high speed clock

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You can use an external clock source that is programmable.

An external clock source that is programmable? Can you give a example(the chip's name)?

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One option is to use a direct digital synthesizer (DDS). Analog devices has many devices.

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As you know,I am designing an oscilloscope so the sample rate Varies greatly.

I design divider that is programmable using FPGA to control ADC clock.

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The sample rate of the ADC does not have to vary at all. You can vary the sample rate once you have the data on the FPGA using multi-rate sampling and digital filtering. While this may seem more complex, it may in fact be simpler, in that your ADC operates at a fixed frequency. For example, I run my 1GHz ADCs at 1GHz all the time. Digital filters are then used to generate 250MHz, 125MHz, etc, down to 2MHz sampling modes.

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Equivalent sampling is to use low-frequency sampling high-frequency signals.

I use the sequential sampling technique. sampling a point a cycle of signal, and delay a slight time(slight delay determines the sampling rate ). I use the 200M counting clock signalto get signal's period. And I design a state machine get the clock to control AD.

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Ok, glad to hear you understand how to make this work. However, this scheme will not work with any old 1MHz ADC. The 1MHz ADC must have an input analog bandwidth in excess of 100MHz and the ADC clock plus aperture jitter must meet the requirements I state above, or you must have a wide bandwidth track-and-hold (T/H) or sample-and-hold (S/H) in front of your ADC, with in excess of 100MHz of bandwidth clocked by a clock with the jitter requirements I state above.

You cannot avoid the input bandwidth requirement, and having a very clean clock source.

Why are you trying to use a 1MHz ADC? Does it meet the requirements I have pointed out?

Cheers,

Dave