how tooutput a high speed clock

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I need change the ADC clock to control sampling rate(we are designing a digital storage osciioscope). I just need a 1M time Sampling clock and 200M Equivalent Sampling,so I need a clock from FPGA. I just change the ADC clock's frenquency to get different sampling rate.

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If you are designing an oscilloscope, then the number of bits in your ADC, and the highest sampling frequency determine your required jitter. For example, if your ADC is 12-bits, and the maximum frequency is 100MHz, then the maximum jitter (clock plus ADC) is

tj < 1/(2*pi*fmax*2^B ) = 1/(2*pi*100MHz*2^12) = 0.39ps

Which is a difficult specification to meet. You would generally use an external clock source (low jitter crystal or VCO) to implement such a clock.

Why do you want to implement an equivalent sampling scheme at 200MHz? This is a low enough frequency that you can implement a real-time sampling oscilloscope. There's no advantage in trying to achieve equivalent time sampling at this frequency, as you still need to meet the analog input bandwidth and jitter specification of a real-time sampling scope.

Cheers,

Dave