how tooutput a high speed clock

FPGA IO signals can't be good or bad as such. They undergo the general rules of interfacing high speed digital signals. As you are talking about 1 MHz clock frequency, I guess, the problem may be, that you aren't familar with logic signals in the FPGA typical speed range.

A good standard to get clean square waves is using source side impedance matching. Presumed you have a cable or PCB trace with e.g 50 to 80 ohm characteristic impedance, supplement the FPGA pins output impedance with a series resistor to make the sum match the characteristic impedance. The method will work with a low to moderate capacitive load.

For a detailed discussion, you should tell more about the problem you're facing. Posting waveform photos isn't a bad idea.

P.S.: For high performance requirements, e.g. to achieve low jitter, it may be reasonable, to send the clock signal using the LVDS IO standard and place a LVDS receiver near the load. This will effectively eliminate most common mode interferences possibly present in a highly populated digital circuit.