Forum Discussion
Honored ContributorHow to simulate the FPGA neural network in Altera
I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simulation items of menu is disabled. Should it due to absence of installed device --such warning is appered when creating the project or I do not entered the license properly. If the issue is in not installed device, which one can I use for my student work, how much space it could take. Can I use the web-edition for this purposes, with or without device?
And the next set of questions relates to the ocding of logical circuit in Altera or Modelsim (which one could I use-- now I have just Model-Sim free edition). The logic circuit should sort analog signals. The other components of circuits is adders with 2 addings and one substraction, and one with adding of all N signals (or non-binary numbers) the N+2 step functions (comparators of amplitude of signals with some x), and one multiplicator and one integrator. So definitive question is the concept and specific of neural networs with back-propagation method in HDL, and other ones is concerning the converting decimal numbers to binary ones (or it could be allowed to be binary from the start), how implement of multiplication for the big coeficent, how the comparator works in Verilog/VHDL, and the most unsure --about integrating the function. I do not exactly even know what is the role of integrator in logic circle (in this case it is connected with the multiplicator and authors even jjust whol ethe whole structure --inverting integrator --*(-Alpha)). Where I could find such examples in VHDL, but it would be better in Verilog, that I studied something. What structure and size of teh whole programming module should be if N (number of sorted items) is 5-6...67 Replies
Altera_Forumhttp://www.alteraforum.com/forum/showthread.php?p=92866 http://www-mtl.mit.edu/courses/6.111/labkit/simulation.shtml -- here is about modelling testbench (despite the first item is not very understandable). Is it really automatically to make testbecnh in Verilog or at least in VHDL in ModelSim. And what WTA net you included, what is its algorithm? I need to realize my olgorithm. And one important question -- can I simulate my algorithm in Xilinx System Generator? If so -- what part of Vivaro I need to download -- as the whole bunch of 5gb is to much -- but is it possible to use just needde for HDL generated code simulation?
- Altera_Forum
Since I found this project pretty interesting, I'm going to provide you with the generated vhdl code. It is up to you to figure out how to use it, and how to build the testbench and modelsim simulation.
The code is for 1 Winner Takes All neural net with 6 inputs. If you want more than 1 winner, then you would have to regenerate the vhdl on your own. The DSP builder model is also attached. - Altera_Forum
http://www.alteraforum.com/forum/attachment.php?attachmentid=10775&stc=1 I think if you would provide FPGA wave (signal) of this circuit it would helpful not just for me but also for those people that would see my presentation. I have said a few of them have skills in Xilings so they value it enough. Then I would by myself created the testbench for another case or in another language and produced here. It is even interesting here. Despite the image of disrete signal show me a few about nature of the sognal -- for example why all waves in this signal is the same level -- what they shows --a how display decreasing signal like in Simulink?
- Altera_Forum
And I also am better at least theoretically in Verilog and it is prefferable
- Altera_Forum
I would try to do it by myself but have no time particularly for VHDL testbench.
Untill tomorrow I would like to have the HDL realization of my simulink design to show it on my presentation -- especially it would be fine to see on Xilix, despite other options would be good. Then I will try to do it be myself. - Altera_Forum
So what exactly do you want me to do? I can generate you the DSP model and the VHDL code from that... but you won't learn anything in the process.
- Altera_Forum
Just now I opened FP toolbox in MAtlab 2009a but really it is diffuclt to grasp
hwo to make automatical conversion to Fixed Point? If I should do it by hand HDL testbech -- are there ready example that I would cahnge a bit for my task --how much number of lines I should wright? And I should present my work in 2-3 days so I want to present also the digital version taht i got in Simulink-- in Altera or Xilinx. The last think is very valuable there. - Altera_Forum
The HDL testbench can be made by hand. It is simply 1 file that instantiates your design, and sets up the clock, resets, inputs and outputs. If you have the basic, free, version of Modelsim all files have to be written in the same language. So DSP builder outputs VHDL, therefore you testbench has to be in VHDL. This is a pain... for me at least because I'm much better in Verilog than VHDL.
But before you do the testbench, were you able to make your HDL files from the digital version of the neural net design? - Altera_Forum
So what about HDL testbench. How difficult is it to do it manually? Could I do it automatically?
In Altera, ModelSim, DSP? System Generator seems to have. but I really have no time to download the last and is it possible to use it without Xilinx FPGA? - Altera_Forum
