How to simulate the FPGA neural network in Altera

Ok you definitely need to upgrade matlab. Also in the simulation configuration panel, you are probably still using "Variable Step". You can change that to "Fixed Step" then use 0.001.

Sample Time is in "seconds". So Sample time of 1 = 1 second per step. Sample Time of 0.001 is 1/1000 of second per step. Sample Time of -1 mean use the same sample time as the block before or as set in the configurations.

Yeah your simulimk/matlab is so old that I can't even back convert it that far.

My Simulink 5.0 tells me that your MAtlab 6.5 version is newer then mine -- 6.5.0.18091 (R13). Where I should note 0.001 -- in Max, Min, Initial Step in Simulation Parameters? I thought early iy should be in Sample Time as by default it seems to be 1 (inherited --> -1). But it doesnot work now.

But I located my Mdl file to convert it to VHDL and test it .. in DSP, ModelSim, SystemGenerator

OK i see what is going on. When you do discrete functions you need to set up the proper fixed time step. If the time step is too large, you will not get the right results. I set the time step to less than 0.001 (i like 0.0001 better, the is 10kHz) and my discrete results match the continuous results. Fixed time step is set in Simulation > Configuration Parameters.

I am attaching my discrete model. You are using Matlab 6.5 correct? I am attaching a 2009a version and a 6.5 version. I use 2013b so i have to back convert. Hopefully one of these files works for you.

So can I generate the HDL just with Filter Design Coder from Matlab2009 -- I have now--it seems generate, and verify on HDL testbench but in Model-Sim.

Here is my continious time model-- it could be change to discret time--but the results is just simple line and also vertical line so something incorrect, so i left continous time--http://s000.tinyupload.com/?file_id=18188888348335316509

First express your integrator in discrete domain (z-domain). Yes you have to use discrete time. You need to set up the fixed time step as well.

It seems that you really want to use HDL coder. That is fine. In HDL coder you can generate code and simulate your design. However, you will not be able to verify that your model has been accurately converted to HDL.

You will need to simulate your HDL in Modelsim or ActiveHDL to validate the conversion. (This is not trivial to do).

I thought HDL coder can only make VHDL code, but if it can make Verilog code then go for it. DSP builder can only make VHDL. Either way, the code will probably be difficult to analyze by hand since the conversion process will generate very non-descriptive register name. It is not easy to read through the generated HDL code.

But to start, first you need to make a continuous simulink model and verify its functionality. Then post it here and I can tell you what to do next.

So what I should do with my continous time integrator block with simulink? AMybe just to change to Discrete time? Or I need to add some clock to such integrator or just change the block?

I also found the Filter HDL Coder in Matlab 2009 -- what is the abilities of such programm--can I generate and simulate HDL code, or just generate?

I also read about VHDL and VErilog in HDL coder -- why you talk about just of VHDL?

To add one thing to krasners post: Mixing VHDL and Verilog cannot be done in the web version of Quartus. So if you use that to actually synthesize the hardware it will not work.

[edit]This is not true, see next post for explanation[/edit]

Lots of questions here. I will try to answer as best I can.

HDL coder works with, i think, Matlab 2012a and beyond. I use Matlab 2013b. HDL coder and DSP builder both generate only VHDL code. However, as I've said before, since HDL coder is vendor independent - the code it produces is very generic. It would be very difficult to optimize this code by hand, and will depend on the HDL synthesizer's ability to properly allocated resources. DSP builder is more optimal for Altera devices since it was design by Altera for use with their FPGAs. Therefore, they know the architecture of the chip. Either way you need to upgrade you Matlab to a newer version.

When you build with HDL coder or DSP builder you need to set up a base clock. This is because any discrete system needs a time step. It can be 20ns for example, that would require a 50MHz clock which is not a fast speed for FPGAs. You can use Matlab functions, like c2d( ) and tf2sos ( ) to convert your S - domain transfer functions to Z - domain. The system you create using DSP blockset will look a lot like the Simulink design, but you will be using only the parts provided in the DSP Blockset library.

Once you generate VHDL code from DSP builder, you can mix it with Verilog files if you want. The synthesizer does not care, as long as all modules are properly connected. The easiest approach would be to import your VHDL code to Qsys and integrate it with your other modules.

You cannot use Xilinx system generator with Altera FPGAs, only with Xilinx FPGAs. I assume the tool and the amount of work required is the same. Yes, the process of going from continuous to discrete to HDL is tedious, but it is necessary. IT will depend on the complexity of your design.

I do not know enough about FPAAs to comment on them. But I think your design is feasible in an FPGA. But as I said before, you MUST convert to discrete domain; you will not be able to use continuous time functions.

If you want, you can post your Simulink model (the continuous one) and I can take a look at it.