How to simulate the FPGA neural network in Altera

First express your integrator in discrete domain (z-domain). Yes you have to use discrete time. You need to set up the fixed time step as well.

It seems that you really want to use HDL coder. That is fine. In HDL coder you can generate code and simulate your design. However, you will not be able to verify that your model has been accurately converted to HDL.

You will need to simulate your HDL in Modelsim or ActiveHDL to validate the conversion. (This is not trivial to do).

I thought HDL coder can only make VHDL code, but if it can make Verilog code then go for it. DSP builder can only make VHDL. Either way, the code will probably be difficult to analyze by hand since the conversion process will generate very non-descriptive register name. It is not easy to read through the generated HDL code.

But to start, first you need to make a continuous simulink model and verify its functionality. Then post it here and I can tell you what to do next.