How to Interface 10M04SCU169 with Host processor

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What micro are you using? How many I/O lines does it have for memory mapped peripherals?

Yes - you will be able to connect the micro to any GPIO on the FPGA. There are no specific pins on the FPGA that you must use.

Cheers,

Alex

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Micro is RX631 from Renesas make and 169 BGA package

Could you please explain with example -that how to connect FPGA 10M01SCU to RX631 Micro

pls share the other links also

Do we required Wait signal for the interface?

How many address and data requried ?

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Within limits, however. If the micro has 3.3V I/O, and the FPGA has multiple I/O banks, you must the I/Os populated in a compatible voltage bank.

You may be using 1.8V or 2.5V I/O for some other interfaces, so those banks may not be compatible with a 3.3V I/O CPU interface requirement.

So some planning will be necessary to choose where you connect the I/Os, but as indicated you will have a lot of flexibility of choice within an I/O bank.

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Thanks a Lot

Micro is RX631 169 BGA package from Renesas, Working on 3.3V VDD

FPGA is also working on single supply 3.3V voltage

RX631 is having 2 WAIT signal, 6 Chip Select, Write and Read signals and 24 address and 16 data lines

We have LAN9252 ESC interfaced to RX631 Micro by 4 address line and 15 Data Line

So, please guide us about How to interface FPGA to Micro and LAN9252 to FPGA using address and data line

i have attached pin mapping connection diagram

pls. revert back with suggestion and comments

--- Quote Start ---

What micro are you using? How many I/O lines does it have for memory mapped peripherals?

Yes - you will be able to connect the micro to any GPIO on the FPGA. There are no specific pins on the FPGA that you must use.

Cheers,

Alex

--- Quote End ---

Within limits, however. If the micro has 3.3V I/O, and the FPGA has multiple I/O banks, you must the I/Os populated in a compatible voltage bank.

You may be using 1.8V or 2.5V I/O for some other interfaces, so those banks may not be compatible with a 3.3V I/O CPU interface requirement.

So some planning will be necessary to choose where you connect the I/Os, but as indicated you will have a lot of flexibility of choice within an I/O bank.

What micro are you using? How many I/O lines does it have for memory mapped peripherals?

Yes - you will be able to connect the micro to any GPIO on the FPGA. There are no specific pins on the FPGA that you must use.

Cheers,

Alex

Thank you,

But still, i am not clear about the number of minimum I/O line

Could you please let me know minimum I/O pins required to interface FPGA and Microcontroller

Can I connect any I/O pin to MCU for address, data and control lines

OR is there any specific pin for the MCU and FPGA interface?

I am not able to run or check pin planner because of not aware and time limit

if any sample document with of 10M04SCU169 pls. share link

at least share minimum control lines required for interface

Put the FPGA design together and let Quartus help you.

How many control signals is up to you and the constraints of the processor - i.e. what control signals it has to offer. You mention RD and WR. Fine. If this interface is to be shared with other peripherals then a dedicate chip select (CS) for the FPGA will be required too. If it's not shared then you can do without CS.

Once you have an FPGA design Quartus will/can select I/O for you. Depending on any other requirements you have you're probably best guiding it through the pin planner. Keeping the Micro interface to one bank of the FPGA may be advantageous, for example. See this "my first fpga tutorial (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/tt/tt_my_first_fpga.pdf)" for help with the Pin Planner - although there is plenty of other online help out there too.

Cheers,

Alex