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Honored Contributor
Honored ContributorHow to Interface 10M04SCU169 with Host processor
Hello All, I am new in this forum and FPGA device exp. I would like to know how we can interface MAX10 series FPGA to External MCU/ Processor How can we decide the IO lines at FPGA si...
Altera_ForumHonored Contributor
Honored ContributorPut the FPGA design together and let Quartus help you.
How many control signals is up to you and the constraints of the processor - i.e. what control signals it has to offer. You mention RD and WR. Fine. If this interface is to be shared with other peripherals then a dedicate chip select (CS) for the FPGA will be required too. If it's not shared then you can do without CS. Once you have an FPGA design Quartus will/can select I/O for you. Depending on any other requirements you have you're probably best guiding it through the pin planner. Keeping the Micro interface to one bank of the FPGA may be advantageous, for example. See this "my first fpga tutorial (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/tt/tt_my_first_fpga.pdf)" for help with the Pin Planner - although there is plenty of other online help out there too. Cheers, Alex
