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Within limits, however. If the micro has 3.3V I/O, and the FPGA has multiple I/O banks, you must the I/Os populated in a compatible voltage bank.
You may be using 1.8V or 2.5V I/O for some other interfaces, so those banks may not be compatible with a 3.3V I/O CPU interface requirement.
So some planning will be necessary to choose where you connect the I/Os, but as indicated you will have a lot of flexibility of choice within an I/O bank.
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Thanks a Lot
Micro is RX631 169 BGA package from Renesas, Working on 3.3V VDD
FPGA is also working on single supply 3.3V voltage
RX631 is having 2 WAIT signal, 6 Chip Select, Write and Read signals and
24 address and 16 data lines
We have LAN9252 ESC interfaced to RX631 Micro by 4 address line and 15 Data Line
So, please guide us about How to interface FPGA to Micro and LAN9252 to FPGA using address and data line
i have attached pin mapping connection diagram
pls. revert back with suggestion and comments
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