Honored ContributorThere're two nios II SOPC in my design. After compilation of the FPGA design, the SOF file is generated. And for two nios II processor, I have edited the software and after compilation, two ELF image files are generated. Here is my question, how to combine them together to generate the JIC file for programming? Is anybody can give the detailed steps for this procedure? Thank you very much!
Honored ContributorNobody knows about this?
Honored ContributorAs per i know and u said that SOF is generated so from SOF you will be able to generate JIC
Just keep updated two elf files ( by buidling nios projects),compile your design in quartus and make jic from "convert programming file" in quartus gui.Honored Contributorassuming you are using EPCS as configuration and as the reset vector in both processors, i think you will need a custom bootloader. the EPCS bootloader reads the location of the end of the .sof in EPCS, and starts reading data immediately after. you can probably use this for one of the Nios processors, but the other will need a custom bootloader with a partitioning scheme
Honored ContributorThank you for your reply. Now I have found the answer. I configured the processors boot from on chip memory, so when I compile the NIOS II software, there're two on_chip_mem_xx.hex file automatical generated in the folder of the whole project. So when I compile the whole project, the two .hex file will be compiled into .sof file. Then I convert the .sof file into .jic file and download it into the board, both processors can work normally. Is the procedure I describe above correct?
Honored Contributoryes, if you are booting from on-chip memory it should be pretty straight forward. you should be able to check the fitter report to see that the two on chip memories were initialized from the expected .hex files
Honored ContributorThank you all!
