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Altera_Forum
Honored Contributor
Honored ContributorHow to generate 32-bit Counter Values using NIOS II Processor?
Hi,
I am having Verilog code for 32-bit Counter Values, and also i know to compile in Quartus. But my actual requirement is, i need to implement the counter design from Quartus through NIOS interface. Please tell me how it is possible ? What interconnect i need to cho0se in QSYS ?:( module ThirtyTwobit_counter (
out , // Output of the counter
clk , // clock Input
);
input clk;
output out;
reg out=0;
//-- Sensitive to rising edge
always @(posedge clk) begin
//-- Incrementar el registro
out <= out + 1;
end
endmodule4 Replies
Altera_ForumHi,
I have built the 8-bit Counter design in Qsys and tried to add the BD design in Quartus. Then through the c code i thought to initialize the counter in NIOS processor. I am using CYCLONE V FPGA, and Quartus Prime edition. But in Block design, output [7:0] port is missing. Please anyone guide me in this task i dont know where i am making mistake.
As above code, i have built the qip system and generated the qsys component. https://www.alteraforum.com/forum/attachment.php?attachmentid=15670module Eight_counter ( out , // Output of the counter clk , // clock Input ); input clk; output out; reg out=0; //-- Sensitive to rising edge always @(posedge clk) begin //-- Incrementar el registro out <= out + 1; end endmodule- Altera_Forum
First, you did not create the counter in Platform Designer. That's just a parallel I/O component you show in your system design. To add the counter as a component in Platform Designer, you have to turn it into a Platform Design component using the Component Editor, specifying the HDL file and setting up the interface(s).
Second, I'm not sure how you are creating that block symbol (.bsf). How did you do it? See this training to learn about the component editor and the standard interfaces used by Qsys/Platform Designer: https://www.altera.com/support/training/course/oqsys3000.html - Altera_Forum--- Quote Start --- First, you did not create the counter in Platform Designer. That's just a parallel I/O component you show in your system design. To add the counter as a component in Platform Designer, you have to turn it into a Platform Design component using the Component Editor, specifying the HDL file and setting up the interface(s). Second, I'm not sure how you are creating that block symbol (.bsf). How did you do it? See this training to learn about the component editor and the standard interfaces used by Qsys/Platform Designer: https://www.altera.com/support/training/course/oqsys3000.html --- Quote End --- Thanks for your response. In Youtube tutorial, i have followed the above process. They made the counter design so simple I have followed the link https://www.youtube.com/watch?v=pkyfcbtalpw (https://www.youtube.com/watch?v=pkyfcbtalpw)
- Altera_Forum
Besides the fact that video is about SOPC Builder, a tool that is no longer in the software, I don't see anything there about creating a counter.
