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Altera_Forum
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7 years ago

How to generate 32-bit Counter Values using NIOS II Processor?

Hi, I am having Verilog code for 32-bit Counter Values, and also i know to compile in Quartus. But my actual requirement is, i need to implement the counter design from Quartus through NIOS ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

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First, you did not create the counter in Platform Designer. That's just a parallel I/O component you show in your system design. To add the counter as a component in Platform Designer, you have to turn it into a Platform Design component using the Component Editor, specifying the HDL file and setting up the interface(s).

Second, I'm not sure how you are creating that block symbol (.bsf). How did you do it?

See this training to learn about the component editor and the standard interfaces used by Qsys/Platform Designer:

https://www.altera.com/support/training/course/oqsys3000.html

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Thanks for your response. In Youtube tutorial, i have followed the above process. They made the counter design so simple

I have followed the link https://www.youtube.com/watch?v=pkyfcbtalpw

(https://www.youtube.com/watch?v=pkyfcbtalpw)