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Honored Contributor
Honored ContributorHow to generate 32-bit Counter Values using NIOS II Processor?
Hi, I am having Verilog code for 32-bit Counter Values, and also i know to compile in Quartus. But my actual requirement is, i need to implement the counter design from Quartus through NIOS ...
Altera_ForumHonored Contributor
Honored ContributorHi,
I have built the 8-bit Counter design in Qsys and tried to add the BD design in Quartus. Then through the c code i thought to initialize the counter in NIOS processor. I am using CYCLONE V FPGA, and Quartus Prime edition. But in Block design, output [7:0] port is missing. Please anyone guide me in this task i dont know where i am making mistake.
module Eight_counter (
out , // Output of the counter
clk , // clock Input
);
input clk;
output out;
reg out=0;
//-- Sensitive to rising edge
always @(posedge clk) begin
//-- Incrementar el registro
out <= out + 1;
end
endmodule 
