Forum Discussion
Honored ContributorHow to find largest value and its position in memory array?
As attachment... the memory array contains continuous input at every positive edge clock... these inputs are the outputs from the Altera FFT core... then i need to find the peak and its location... please help!!! thanks alot! from the attachment, the peak should be 45 and at memory_array [2].... and they should be shown at the outputs...
26 Replies
Altera_Forumhaven't you already done that as evident from your sim waveforms.
You will need a time machine to do that (internal delays)- Altera_Forum
Hi Kaz... i have another question to ask... as attached picture.... if i have the data_in like that, started at a "later" positive edge clock, i want it to be outputted at the first positive edge clock as shown in d_out, do you know how to do that?
- Altera_Forum--- Quote Start --- okok... i understood this... but i need the waveform show only the largest value without showing the previous smaller values... never mind, i try to find solution myself... thanks so much anyway :) --- Quote End --- The waveform displays values of the node(max_val) so you will always see its values from time zero. you can add further node saying if val = 255 then max_final = 255 but I haven't got a clue what use this is going to be.
- Altera_Forum
okok... i understood this... but i need the waveform show only the largest value without showing the previous smaller values... never mind, i try to find solution myself... thanks so much anyway :)
- Altera_Forum
once value 256 comes in it will displace any lower value at max_val and will stay so until a higher value comes in and kicks it out
- Altera_Forum--- Quote Start --- Just use my above code. The max_val updates and stores din by itself until it is updated (if at all). I am sorry I have not done verilog for years so can't help directly at code level. Yourlast code and waveforms looks ok to me --- Quote End --- Ya the last code is ok i think... but is it posibble to output only the max_value "256" and location "6" throughout the waveforms?
- Altera_Forum
Just use my above code. The max_val updates and stores din by itself until it is updated (if at all).
I am sorry I have not done verilog for years so can't help directly at code level. Yourlast code and waveforms looks ok to me - Altera_Forum
now i change to these codes and the output as shown in picture attachment...
input wire Enable; input wire [9:0] d_in; output reg [9:0] max_value; output reg [2:0] max_location; reg [2:0] Q; initial begin max_value = 0; end always @ (posedge clock) begin if (Enable) begin if (d_in > max_value) begin max_value <= d_in; max_location <= Q; end Q <= Q + 1; end end endmodule - Altera_Forum--- Quote Start --- What another way? It is same one I am telling you since last year!! and your code : why do you keep using the wrong signal name: why do you use max_val_tmp, I did not say that. --- Quote End --- last year?? i just joined today... if i didn't create a temparory reg "max_val_tmp" how can keep the number for comparing with the next number?? if you don't mind to edit my whole codes, so i don't make any mistakes again won't ask you anymore??
- Altera_Forum--- Quote Start --- Thank you Kaz for your time :) **p.s. I need to write d_in into mem_array[Q] so that i can keep track on its location right? **another way i found something: "develop a verilog model for a peak detector that finds the maximum value in a sequence of 10-bit unsigned integers. a new number arrives at the input during a clock cycle when the data_en input is 1. if the new number is greater than the previously stored maximum value, the maximum value is updated with the new number; otherwise, it is unchanged. the stored maximum value is cleared to zero when the reset control input is 1. both data_en and reset are synchronous control inputs." --- Quote End --- What another way? It is same one I am telling you since last year!! and your code : why do you keep using the wrong signal name: why do you use max_val_tmp, I did not say that.
