Forum Discussion
Altera_Forum
Honored Contributor
12 years agonow i change to these codes and the output as shown in picture attachment...
input wire Enable; input wire [9:0] d_in; output reg [9:0] max_value; output reg [2:0] max_location; reg [2:0] Q; initial begin max_value = 0; end always @ (posedge clock) begin if (Enable) begin if (d_in > max_value) begin max_value <= d_in; max_location <= Q; end Q <= Q + 1; end end endmodule