Hi, Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing? for the set_input_delay and the set_output_delay,what time relation does it tell the FPGA?

First, that ODDR module on fp1_co is not needed. Second, you should also use a PLL on FPGA2 if possible. You need to set I/O constrains on the two FPGAs as normal. In the case of FPGA1, this means creating a derived clock on the fp1_co port and setting the output delays referenced on that clock. In the case of FPGA2, you create a base clock on fp2_ci and set the input delays referenced to that clock. The trick is that you need to keep the following relationship: fp1_max_output_delay + fp2_max_input_delay = clock period fp1_min_output_delay + fp2_min_input_delay = 0 This will be an iterative process. I'd start by with fp1_max_output_delay = fp2_max_output_delay = clock_period/2 and fp1_min_output_delay = fp2_min_input_delay = 0 and see what I get and then adjust as needed.

--- Quote Start --- First, that ODDR module on fp1_co is not needed. Second, you should also use a PLL on FPGA2 if possible. You need to set I/O constrains on the two FPGAs as normal. In the case of FPGA1, this means creating a derived clock on the fp1_co port and setting the output delays referenced on that clock. In the case of FPGA2, you create a base clock on fp2_ci and set the input delays referenced to that clock. The trick is that you need to keep the following relationship: fp1_max_output_delay + fp2_max_input_delay = clock period fp1_min_output_delay + fp2_min_input_delay = 0 This will be an iterative process. I'd start by with fp1_max_output_delay = fp2_max_output_delay = clock_period/2 and fp1_min_output_delay = fp2_min_input_delay = 0 and see what I get and then adjust as needed. --- Quote End --- Thank you for your reply.And I still have some questions to ask. 1&#12289;If I don't use the ODDR module on fp1_co,how do I let the output delay be as same as possible between fp1_co and fp1_do relative to clk1? Or rather that it is unimportant. 2&#12289;Is it more better to use PLL on FPGA2?How does the FPGA shift the clock or the data to reach better timing? 3&#12289;for set_output_delay(max),which time in TdelayX(X=1~5) does it tell the FPGA1?And How are the TdelayX(X=1~5) applied in Atera FPGA design? 4&#12289;for set_output_delay(min),which time in TdelayX(X=1~5) does it tell the FPGA1?And How are the TdelayX(X=1~5) applied in Atera FPGA design? 5&#12289;for set_input_delay(max),which time in TdelayX(X=6~9) does it tell the FPGA2?And How are the TdelayX(X=6~9) applied in Atera FPGA design? 6&#12289;for set_input_delay(min),which time in TdelayX(X=6~9) does it tell the FPGA2?And How are the TdelayX(X=6~9) applied in Atera FPGA design? 7&#12289;How do you confirm whether your timing constraint is the best?by post_sim? or by other way?

--- Quote Start --- Hi, Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing? for the set_input_delay and the set_output_delay,what time relation does it tell the FPGA? --- Quote End --- Using DDR and PLL may not be required in your case but you can keep your design as such then I will do the following: The fpga1 can send data and clk aligned readily and all you need is set max and min output delay to zero implying there is no tSU/tH requirement so the fitter maintains the data clock alignment. At fpga2 assume min tCO = -2ns & max tCO = +2ns then set max input delay to about +2ns and min delay to -2ns then the fitter will try avoid the edge area and hopefully centre data away from clock edges. Only if it fails then you can use PLL here.

caobaiyu, 1. Trying to manually adjust delays by adding modules to your design is, generally, a bad idea for bunch of reasons: tools tend to optimize those things away or change the way they're placed. And of course, you have process/voltage/temperature variations. The best way is simply to correctly constrain your design and let the tools do their job. 2. There's a (fairly big) delay between the clock delivered to the FPGA pin and the clock delivered to the flip-flops inside the FPGA, caused by the FPGA clock distribution tree. The PLL can compensate this delay by using the clock delayed by the clock tree as feedback clock. This will cause the clock delivered to the flip-flops to be phase aligned with the clock at the FPGA input pin. Input/Output delays tell the tools about the delays/requirements of the system that surrounds the FPGA. 3: set_output_delay -min xx -clock clk [get_ports fp1_do] tells the tools that, after leaving the FPGA1 pins, fp1_do will be delayed by a minimum of xx ns and then be captured at the rising edge of clk 4: set_output_delay -max XX -clock clk [get_ports fp1_do] does an equivalent thing Put in another way, it's telling the tools that fp1_do is going to flip-flops which operate on the rising edge of clk and have a tSU of XX ns and a tH of -xx ns. 5,6: set_input_delay -min yy -clock clk [get_ports fp2_di] tells the tools that fp1_di will have a minimum delay of yy ns. Equivalent thing for max. Again, put in another way, it's telling the tools that fp2_di is produced by flip-flops operating on the rising edge of clk and have min_tCO of yy ns and max tCO of YY ns. In case of doubt, draw a timing diagram. The tools will then take this information into account and try to optimize the design inside the FPGAs to make sure that all timing requirements are respected. 7. If your constrains meet the relationship I wrote above and TimeQuest says timing requirements are met, then it's OK. You can then try to look at the I/O timings slack in both FPGAs. If one FPGA has large slacks and the other small ones, maybe you should change the constrains a bit to improve it.

--- Quote Start --- Using DDR and PLL may not be required in your case but you can keep your design as such then I will do the following: The fpga1 can send data and clk aligned readily and all you need is set max and min output delay to zero implying there is no tSU/tH requirement so the fitter maintains the data clock alignment. At fpga2 assume min tCO = -2ns & max tCO = +2ns then set max input delay to about +2ns and min delay to -2ns then the fitter will try avoid the edge area and hopefully centre data away from clock edges. Only if it fails then you can use PLL here. --- Quote End --- Thank you for your reply.And It seems that your timing constraint doesn't satisfy the following relationship mentioned by rbugalho. fp1_max_output_delay + fp2_max_input_delay = clock period fp1_min_output_delay + fp2_min_input_delay = 0 So you have diffrent thought about that?

How to do the timing constraint? | Altera Community

22 Replies

Altera_Forum
Honored Contributor
13 years ago
Yep.

There are two steps to this.
First, you need to set constraints that ensure that your design will work if they are met.
Second, when the constraints aren't met, you need to modify your design. Ie, use the PLL to shift a clock phase.
And of course, it's not always possible to meet the constraints.

In most applications, the I/O constrains are fixed by the system outside your FPGA,
In this particular case, you have two FPGAs and thus you also have the freedom to shift constraints around to make them easier to meet.
Altera_Forum
Honored Contributor
12 years ago
Hello.
I have encountered problems on the following timing constraint.
The case is draw in the attachment.
I do timing constraint as follows.
creat_generated_clock -add -name {SysClk} -source [get_pins {*|inclk[0]}] [get_pins {*|clk[0]}]
set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[0]}] [get_ports {D[*]}] -add_delay
set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[1]}] [get_ports {D[*]}] -add_delay
set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[2]}] [get_ports {D[*]}] -add_delay
set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[3]}] [get_ports {D[*]}] -add_delay
But the timing constraint is ignored for the reason as said in the tool.
"the A[0] is not clocked by the clock specified in set_input_delay/set_out_delay -clock options."(I can remember only these,maybe something is missing.)
So,why the warning occurs?And how to do timing constraint at this case?

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How to do the timing constraint?

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