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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to do the timing constraint?

Hi, Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing? for the set_input_delay and the set_output_delay,what time relation does it tell ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hello.

I have encountered problems on the following timing constraint.

The case is draw in the attachment.

I do timing constraint as follows.

creat_generated_clock -add -name {SysClk} -source [get_pins {*|inclk[0]}] [get_pins {*|clk[0]}]

set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[0]}] [get_ports {D[*]}] -add_delay

set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[1]}] [get_ports {D[*]}] -add_delay

set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[2]}] [get_ports {D[*]}] -add_delay

set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[3]}] [get_ports {D[*]}] -add_delay

But the timing constraint is ignored for the reason as said in the tool.

"the A[0] is not clocked by the clock specified in set_input_delay/set_out_delay -clock options."(I can remember only these,maybe something is missing.)

So,why the warning occurs?And how to do timing constraint at this case?