How to do the timing constraint?

Yep.

There are two steps to this.

First, you need to set constraints that ensure that your design will work if they are met.

Second, when the constraints aren't met, you need to modify your design. Ie, use the PLL to shift a clock phase.

And of course, it's not always possible to meet the constraints.

In most applications, the I/O constrains are fixed by the system outside your FPGA,

In this particular case, you have two FPGAs and thus you also have the freedom to shift constraints around to make them easier to meet.