Altera_Forum
Honored Contributor
Honored ContributorHow to connect two ddrs in a cyclone iii?
Hi,
I plan to use two absolute ddrs in my system. And I want to connect them in column banks and row banks,is it viable?Forum Discussion
4 Replies
Altera_Forum--- Quote Start --- Hi, I plan to use two absolute ddrs in my system. And I want to connect them in column banks and row banks,is it viable? --- Quote End --- If your ddrs have the same size you can double your column banks (for example). The highest bit you can use as an enable signal. If it is set you can enable ddr1. Otherwise you enable ddr2. Don´t forget to multiplex the output data.- Altera_Forum
You didn't say, if you need to operate the DDR cores independently. And no bit width information. Generally, the CIII hardware handbook has an overview of available DDR interface resources with respective maximum speed for row and column banks.
- Altera_Forum--- Quote Start --- You didn't say, if you need to operate the DDR cores independently. And no bit width information. Generally, the CIII hardware handbook has an overview of available DDR interface resources with respective maximum speed for row and column banks. --- Quote End --- Thank all replys. Yes, I need two independent DDR cores and the bit-width of them are all 16 bits. I want to sure that I can place the cores in BANK 3,4 and BANK 5,6 respectively?
- Altera_Forum
According to the overview in hardware handbook, this should work, I suggest to write a test design (e.g. two instances of the Altera test driver) and compile with the intended pin assignments before starting the PCB. You have to keep several constraints, e.g. I/O distance rules, and maximum number of voltage referenced pins in a bank.
