How to accumulate variable using submodule

--- Quote Start ---

I am trying to model an equation of the type:

x=bx+c in Verilog.

I've written a module which takes input 'x' and gives output 'bx+c'. However since the input and output out of a submodule have to be nets(wires), this is how I'm trying to model the equation:

Let's say the submodule for 'bx+c' is 'submod1'

I've given the names:

xin--> Input net to submod1

xout-->Output net from submod1

xreg-->A register in top-module for storing and reading values from submod1

always @(xout)

begin

case(rst) //rst, reset signal for resetting the value to 0

1'b0:if(xout!=32'hx) //Copy xout to xreg only if the signal is stable

xreg=xout;

else

xreg=0;

1'b1:xreg=0;

endcase

end

assign xin=xreg;

Can anyone see any problems with this code? Any help is most appreciated.

--- Quote End ---

Hi,

I would make the design synchronous ( use a clock). Have a look to:

// x=b*x+c

module test (reset, clk, b,c, out);

input reset,clk;

input [1:0] b,c;

output [3:0] out;

reg [3:0] result;

always @(posedge clk) begin

if(reset) result <= 0;

else result <= result * b + c;

end

assign out = result;

endmodule

It is only a simple example. You have to take care about the required output width and the handling of signed numbers if required.

Kind regards

GPK

@pletz, Thanks for reply. However the actual equation involved is a lot more complicated. The actual equation is of the type:

x=x*((a+b)/d)+(x*x-2*(d/b));

and the answer required is of the single precision type. So I'm using Altera's megafunctions to compute the result of the above equation. I made the submodule, 'submod1' which takes all the inputs required for the equation i.e. x,a,b,d and gives the result of the expression, altera's megafunctions are instantiated and used inside this module. Since the output from submod1 has to be of type net(wire), I have to declare a register in toplevel module to store the value of 'x' given by 'submod1'.

To give you a brief idea here is the structure of code:

*************************************

module topmodule(

input ports,

output ports);

wire [31:0] xin;

wire [31:0] xout;

reg [31:0] xreg;

submod1 instance1(

.clk(clk),

.x(xin),

.a(a),

.b(b),

.d(d),

.result(xout)

);

always @(xout)

begin

case(rst) //rst, reset signal for resetting the value to 0

1'b0:if(xout!=32'hx) //Copy xout to xreg only if the signal is stable

xreg=xout;

else

xreg=0;

1'b1:xreg=0;

endcase

end

assign xin=xreg;

***********************

Do you think this is the correct way to accumulate the variable? I'm mainly concerned about the always block and whether the expression (xout!=32'hx) does what it is supposed to do(avoid copying garbage xout such as 32'hxxxxxxxx to xreg). Hope you can help.

As Pletz suggested, the design won't work if xreg isn't assigned in a clock synchronous always block. The "signal stable" construct doesn't work in synthesis (possibly in simulation).

Alternatively, if the submodule is implementing a register for xout, you can directly and unconditionally assign xout to xin.