How to accumulate variable using submodule

@pletz, Thanks for reply. However the actual equation involved is a lot more complicated. The actual equation is of the type:

x=x*((a+b)/d)+(x*x-2*(d/b));

and the answer required is of the single precision type. So I'm using Altera's megafunctions to compute the result of the above equation. I made the submodule, 'submod1' which takes all the inputs required for the equation i.e. x,a,b,d and gives the result of the expression, altera's megafunctions are instantiated and used inside this module. Since the output from submod1 has to be of type net(wire), I have to declare a register in toplevel module to store the value of 'x' given by 'submod1'.

To give you a brief idea here is the structure of code:

*************************************

module topmodule(

input ports,

output ports);

wire [31:0] xin;

wire [31:0] xout;

reg [31:0] xreg;

submod1 instance1(

.clk(clk),

.x(xin),

.a(a),

.b(b),

.d(d),

.result(xout)

);

always @(xout)

begin

case(rst) //rst, reset signal for resetting the value to 0

1'b0:if(xout!=32'hx) //Copy xout to xreg only if the signal is stable

xreg=xout;

else

xreg=0;

1'b1:xreg=0;

endcase

end

assign xin=xreg;

***********************

Do you think this is the correct way to accumulate the variable? I'm mainly concerned about the always block and whether the expression (xout!=32'hx) does what it is supposed to do(avoid copying garbage xout such as 32'hxxxxxxxx to xreg). Hope you can help.