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Altera_Forum
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16 years ago

How to accumulate variable using submodule

I am trying to model an equation of the type: x=bx+c in Verilog. I've written a module which takes input 'x' and gives output 'bx+c'. However since the input and output out of a submodule hav...
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Altera_Forum
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16 years ago

@fvm thanks for your reply. The problem is that the submodule's output is restricted to being of type net(wire). Could you give a brief code snippet to suggest what might be possible or how could I do this?