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I am trying to model an equation of the type:
x=bx+c in Verilog.
I've written a module which takes input 'x' and gives output 'bx+c'. However since the input and output out of a submodule have to be nets(wires), this is how I'm trying to model the equation:
Let's say the submodule for 'bx+c' is 'submod1'
I've given the names:
xin--> Input net to submod1
xout-->Output net from submod1
xreg-->A register in top-module for storing and reading values from submod1
always @(xout)
begin
case(rst) //rst, reset signal for resetting the value to 0
1'b0:if(xout!=32'hx) //Copy xout to xreg only if the signal is stable
xreg=xout;
else
xreg=0;
1'b1:xreg=0;
endcase
end
assign xin=xreg;
Can anyone see any problems with this code? Any help is most appreciated.
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Hi,
I would make the design synchronous ( use a clock). Have a look to:
// x=b*x+c
module test (reset, clk, b,c, out);
input reset,clk;
input [1:0] b,c;
output [3:0] out;
reg [3:0] result;
always @(posedge clk) begin
if(reset) result <= 0;
else result <= result * b + c;
end
assign out = result;
endmodule
It is only a simple example. You have to take care about the required output width and the handling of signed numbers if required.
Kind regards
GPK
Honored Contributor
