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Altera_Forum
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16 years ago

How to accumulate variable using submodule

I am trying to model an equation of the type: x=bx+c in Verilog. I've written a module which takes input 'x' and gives output 'bx+c'. However since the input and output out of a submodule hav...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

always @(posedge clk) 
begin
if(rst) xreg <= 0;
else xreg <= xout;
end
assign xin=xreg;