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Altera_Forum
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15 years ago

How to accumulate variable using submodule

I am trying to model an equation of the type: x=bx+c in Verilog. I've written a module which takes input 'x' and gives output 'bx+c'. However since the input and output out of a submodule hav...
Altera_Forum's avatar
Altera_Forum
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15 years ago

As Pletz suggested, the design won't work if xreg isn't assigned in a clock synchronous always block. The "signal stable" construct doesn't work in synthesis (possibly in simulation).

Alternatively, if the submodule is implementing a register for xout, you can directly and unconditionally assign xout to xin.