How LEs are aligned

Question

Hello

I have three questions considering about how LEs are aligned and placed.

(1)

I want to know how LEs are aligned "physically."

Because by the default of Quartus II LEs are sometimes placed far from the I/O elements which are intented to be used, I think the alignment you can see on Chip Planner is not real and real LE alignments should be something different.

(2)

As mentioned above, the default placement of LEs by Quartus II seems weird to me.

So I want to know the principal of the LE placement by Quartus II. There must be some logics about the placement (for there is no "randoms" in computer world).

(3)

I want to know where "unassigned" I/O elements are connected to.

In most ICs, I/O ports have fixed voltage (GND or Vcc) to avoid the through-current to the CMOS.

So what I am thinking is that the unassigned I/O elements must be connected to GND or Vcc.

Any replies are appreciated.

Thanks

altera_forum · Answer

(1) &amp; (2) - Quartus places the LEs using your timing constraints.  If you have none, it may randomly place your first LE far from the pin.  There are a few things you can do to prevent this.  If you setup your timing analysis scripts properly and enable fast input registers (or fast output registers) your design should make a little more sense in the chip planner.  (3) In Quartus: Menus:Assignments-&gt;Device...  Select device and pin options.  There is a selection called "Unused Pins".  This is where you set these.  (Be very careful if you select "As output driving ground".  If your pinout is not setup correctly, your FPGA may get fairly hot.

altera_forum · Answer

Dear kosh271

Thanks for your rapid reply!!

--- Quote Start ---

(1) & (2) - Quartus places the LEs using your timing constraints. If you have none, it may randomly place your first LE far from the pin. There are a few things you can do to prevent this. If you setup your timing analysis scripts properly and enable fast input registers (or fast output registers) your design should make a little more sense in the chip planner.

--- Quote End ---

So Quartus II does not consider anything with respect to place&route unless no constraints are set??

I still feel weird about the randomness... There must be some programs for making the randomness and thus the default placement might have some meanings.

Anyway, back to my first question (1), I want to know how LEs are aligned "physically."

Does the Chip Planner reflect the real alignment of LE??

--- Quote Start ---

(3) In Quartus: Menus:Assignments->Device... Select device and pin options. There is a selection called "Unused Pins". This is where you set these. (Be very careful if you select "As output driving ground". If your pinout is not setup correctly, your FPGA may get fairly hot.

--- Quote End ---

I appreciate your kind reply. You solved my question (3).

altera_forum · Answer

Quartus uses a pseudo-random generator to place your elements and stops when your timing constraints are met. So yes if you don't set any timing constraints you will end up with something that looks random.

You have to understand that the place and route algorithm needs to be able to cope with a lot of different situations. On a very simple system it may look obvious where to put the LEs for the best performance, but as the system gets more and more complex, just "putting all the LEs near each other" is no longer a viable option. You need to identify the highest priority signals and ensure that the LEs on those paths are close together and reserve some space for them, while the LEs processing slow or less important signals can be spread around where we have some space. That's why it is very important to define your important signals with timing constraints.

AFAIK the positions shown by the chip planner aren't far from the real locations on the chip.

altera_forum · Answer

Dear Daixiwen

--- Quote Start ---

Quartus uses a pseudo-random generator to place your elements and stops when your timing constraints are met. So yes if you don't set any timing constraints you will end up with something that looks random.

You have to understand that the place and route algorithm needs to be able to cope with a lot of different situations. On a very simple system it may look obvious where to put the LEs for the best performance, but as the system gets more and more complex, just "putting all the LEs near each other" is no longer a viable option. You need to identify the highest priority signals and ensure that the LEs on those paths are close together and reserve some space for them, while the LEs processing slow or less important signals can be spread around where we have some space. That's why it is very important to define your important signals with timing constraints.

AFAIK the positions shown by the chip planner aren't far from the real locations on the chip.

--- Quote End ---

Thanks for your reply.

I now got what Quartus do but have a new question: can't you understand what really Quartus do (or the algorithm of place & route)??

I mean I have to know and explain the reason for the placing of LEs when showing my FPGA to customers and/or my boss.

The answer "Quartus does it" must be avoided... lol

altera_forum · Answer

The question you should rather ask yourself is whether or not the LE placement is relevant information for your boss or customer. It doesn't show anything about your design or the performance. I think it would be a lot more relevant to show them the timing report instead.

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How LEs are aligned

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