How LEs are aligned

Dear Daixiwen

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Quartus uses a pseudo-random generator to place your elements and stops when your timing constraints are met. So yes if you don't set any timing constraints you will end up with something that looks random.

You have to understand that the place and route algorithm needs to be able to cope with a lot of different situations. On a very simple system it may look obvious where to put the LEs for the best performance, but as the system gets more and more complex, just "putting all the LEs near each other" is no longer a viable option. You need to identify the highest priority signals and ensure that the LEs on those paths are close together and reserve some space for them, while the LEs processing slow or less important signals can be spread around where we have some space. That's why it is very important to define your important signals with timing constraints.

AFAIK the positions shown by the chip planner aren't far from the real locations on the chip.

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Thanks for your reply.

I now got what Quartus do but have a new question: can't you understand what really Quartus do (or the algorithm of place & route)??

I mean I have to know and explain the reason for the placing of LEs when showing my FPGA to customers and/or my boss.

The answer "Quartus does it" must be avoided... lol