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Honored Contributor
Honored ContributorHow LEs are aligned
Hello I have three questions considering about how LEs are aligned and placed. (1) I want to know how LEs are aligned "physically." Because by the default of Quartus II LEs are sometim...
Altera_ForumHonored Contributor
Honored Contributor(1) & (2) - Quartus places the LEs using your timing constraints. If you have none, it may randomly place your first LE far from the pin. There are a few things you can do to prevent this. If you setup your timing analysis scripts properly and enable fast input registers (or fast output registers) your design should make a little more sense in the chip planner.
(3) In Quartus: Menus:Assignments->Device... Select device and pin options. There is a selection called "Unused Pins". This is where you set these. (Be very careful if you select "As output driving ground". If your pinout is not setup correctly, your FPGA may get fairly hot.
