How LEs are aligned

Dear Daixiwen,

Sorry for late reply. I've been working on different project and now I'm back to FPGA.

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There isn't a single solution. Of course having the LE right next to the I/O pin is the best solution and it looks better, but as far as Quartus is concerned, having it at the other side of the FPGA is also an acceptable solution if the delay between the LE and the I/O pin is under the limit that you set in your timing requirements.

You might be interested in this very good document (http://www.alterawiki.com/wiki/the_quartus_ii_fitter_and_seed_sweeps) from Rysc that explains a bit how the fitter algorithm works and why it looks like it is random.

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Thanks to the website you taught me, I got the idea of pseudo-random placement.

Plus, more and more I read manuals uploaded by Altera I've come to know how the FPGAs work.

Not much, but a little bit though.

Anyway, thanks for your help.