How LEs are aligned

Dear kosh271

Thanks for your rapid reply!!

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(1) & (2) - Quartus places the LEs using your timing constraints. If you have none, it may randomly place your first LE far from the pin. There are a few things you can do to prevent this. If you setup your timing analysis scripts properly and enable fast input registers (or fast output registers) your design should make a little more sense in the chip planner.

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So Quartus II does not consider anything with respect to place&route unless no constraints are set??

I still feel weird about the randomness... There must be some programs for making the randomness and thus the default placement might have some meanings.

Anyway, back to my first question (1), I want to know how LEs are aligned "physically."

Does the Chip Planner reflect the real alignment of LE??

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(3) In Quartus: Menus:Assignments->Device... Select device and pin options. There is a selection called "Unused Pins". This is where you set these. (Be very careful if you select "As output driving ground". If your pinout is not setup correctly, your FPGA may get fairly hot.

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I appreciate your kind reply. You solved my question (3).