Honored Contributor
Honored ContributorThere isn't a single solution. Of course having the LE right next to the I/O pin is the best solution and it looks better, but as far as Quartus is concerned, having it at the other side of the FPGA is also an acceptable solution if the delay between the LE and the I/O pin is under the limit that you set in your timing requirements.
You might be interested in this very good document (http://www.alterawiki.com/wiki/the_quartus_ii_fitter_and_seed_sweeps) from Rysc that explains a bit how the fitter algorithm works and why it looks like it is random.
