Forum Discussion
Honored Contributorhow does quartus decide to remove logic?
I guess this is a bit of a newbie question (newbie to quartus not hardware design - I'm an old ASIC guy)...
I've crawled through the manual (well, it's 1200 pages long, so I'm sure I missed the discussion), but how does quartus decide to remove logic from a design? I have a big design (1.5M gates, 200K ff), and after mapping, 99% of the logic completely disappears and I am left with a few thousand luts. I found the redundant logic options, noprune (which I am trying now with assorted regs, but so far by putting noprune everywhere except in tasks and functions, I get a hard crash: Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/database/netlist.cpp, Line: 4538 What's confusing especially is that I think I've been careful to make sure data flows in and out of this design.. It simulates by driving data in from outside the chip only (though there may be an initial block somewhere?) I presume that the problem is one of the follow: 1. map doesn't see clocks driven from registers (yes I read about clock generation), so it thinks all clocks a nailed to 0 or whatever... 2. map doesn't see that reset causes powerup fsms to start running.. 3. ??? registers coming up 0 puts everything in a strange state and quartus removes logic thinking it won't start running.. I guess any of the above are fine, but *there's no clue* I can find in the reports or in the quartus that tells me *why* it tossed out all 200,000+ registers ? I suspect that design assistant might, but I haven't quite figured that out either? Any hints much appreciated!11 Replies
Altera_ForumI remember pulling my hair out many moons ago when initially trying to keep logic on FPGA's. You will find that if you provide input into a module and have it drive another module that ultimately hooks to an output pin that your logic will stay in place (albeit sometimes optimized). On occassion, especially with cominatorial logic you will see your logic get squished. It may seem like overkill but if you are using VHDL it is very handy to label things. You can even label if and case statements and it will make things much easier to search for in RTL diagrams and when looking for signal nodes. Maybe you can do something similar in Verilog. 99.99% chance if you are missing modules in the final synthesized or mapped design, somewhere along the data path it didn't make it to an output pin or drive logic, and it's because you didn't hook up a signal properly to an input or output somewhere along the way.
- Altera_Forum--- Quote Start --- 2. map doesn't see that reset causes powerup fsms to start running.. --- Quote End --- i have seen strange optimizations based on the lack of declared power-up values. adding them fixed the issue. i think you can also turn off power-up don't care.
- Altera_Forum
this particular design has a CPU booting off its internal memory (which I am manually loading via code running during reset) which takes data almost directly from the top layer (which doesn't get synthesized away) and drives data back up to the top layer... There are floating nets that I grounded, so I'll start by taking a closer look at those. This particular IP vendor seems to like using IO buffers to implement multiple drivers of control pins (jeez), so there's probably an issue here also...
Thanks for all the ideas.. - Altera_Forum
In short:
any part of design(logic/memory) that doesn't take part in the fun of outside world drive is removed. The design is meant to drive the world outside and not waste time inside doing nothing but heating up... By the way check your system parameters if any. The design may have been meant for different modes(as input) and somebody tested by fixing it internally... - Altera_Forum--- Quote Start --- If you have logic/memory that has no connection to pins, or no reason to connect to pins, then there is your problem. are you making a write-only memory? You need to buy one of these: http://www.national.com/rap/files/datasheet.pdf Basically, it sounds like something is not connected. Just because you have memories that load counters wont be the problem. aslong as these counters address some memory, then eventually has an output that goes to a pin, then fine.The memory doesn not need to directly connect to a pin. --- Quote End --- Thanks for the quick reply. The "Bit Bucket On Silicon" must be selling like hotcakes! Seriously, I am designing an embedded C processor that will drive Avalon peripherals and eventually then drive off chip. How does any embedded processor meet the requirements? My C code is loaded into rams at power on and is used mostly as rom that controls the data flow. Looks like the same old story ==You have to have a completed design FIRST. I wonder how many projects START with a COMPLETE DESIGN?
- Altera_Forum
If you have logic/memory that has no connection to pins, or no reason to connect to pins, then there is your problem. are you making a write-only memory?
You need to buy one of these: http://www.national.com/rap/files/datasheet.pdf Basically, it sounds like something is not connected. Just because you have memories that load counters wont be the problem. aslong as these counters address some memory, then eventually has an output that goes to a pin, then fine.The memory doesn not need to directly connect to a pin. - Altera_Forum
I have a related question about embedded memory. Are there any guidelines/hints about using multiple ram blocks,-- I have rams that load counters that address other rams and have no functional reason to use up pins other than to satisfy synthesis. If I use a multiplexer to make the rams available to pins, is that sufficient? Or will I have testability problems later? Thanks Everyone!
- Altera_Forum
I agree with FvM. IMO, the main causes of logic being optimised away are:
1. Forgetting to connect a logic path ultimatly to an output pin 2. Leaving something accidently disconnected 3. Having FF input/clock stuck at 0/1 or enable stuck at 0 Using a logic generated clock to clock other logic is not going to get synthesised away, but it will cause you major problems. It may pass through the timing analyser this time, but it's likely to fail in future, or on real hardware. Just dont do it - use enables instead. noprune directives are not going to help you. With the above 3 points, all they are going to do, if it does actually keep the no prunne, is eat up a lot of current and not actually do anything, as something unconnected is likely the problem. noprune is usually best for keeping debug logic that you only want to look at in signaltap (even then, its best to send it to an output pin if you can) - Altera_Forum
In addition to Rysc's comment, I think, that your three above guesses why Quartus removes logic, are basically wrong. At least, if standard synthesis options are applied. E.g. driving a clock from a register may possibly cause timing problems, but creates a valid clock anyway. This clock and the logic driven by it would be removed only, if the register is stuck to a constant output, which may be the case in your design.
I completely agree with your assumption of a simple cause, but it's very likely not in the field of synthesis options. - Altera_Forum
Heh, yea I am sure there something completely simplistic going on, but finding it's the hard part :) I have power-up don't cares off, and I'm resynthesizing with hdl_message_level set to the highest (3), so I should have lots to look through when I am done :)
I also asked it to report all the errors (well 5000 of them) not just the first 100.. And the report says that most registers are tossed because the inputs are Vcc or Gnd (fair enough for some registers), other because the input is constant.. It sure sounds like there's some reset issue that is acting differently than simulation. Unfortunately, most of the code is not mine so it's slow working... I'll post what I find...
