how does quartus decide to remove logic?

Heh, yea I am sure there something completely simplistic going on, but finding it's the hard part :) I have power-up don't cares off, and I'm resynthesizing with hdl_message_level set to the highest (3), so I should have lots to look through when I am done :)

I also asked it to report all the errors (well 5000 of them) not just the first 100.. And the report says that most registers are tossed because the inputs are Vcc or Gnd (fair enough for some registers), other because the input is constant..

It sure sounds like there's some reset issue that is acting differently than simulation. Unfortunately, most of the code is not mine so it's slow working...

I'll post what I find...