how does quartus decide to remove logic?

I agree with FvM. IMO, the main causes of logic being optimised away are:

1. Forgetting to connect a logic path ultimatly to an output pin

2. Leaving something accidently disconnected

3. Having FF input/clock stuck at 0/1 or enable stuck at 0

Using a logic generated clock to clock other logic is not going to get synthesised away, but it will cause you major problems. It may pass through the timing analyser this time, but it's likely to fail in future, or on real hardware. Just dont do it - use enables instead.

noprune directives are not going to help you. With the above 3 points, all they are going to do, if it does actually keep the no prunne, is eat up a lot of current and not actually do anything, as something unconnected is likely the problem. noprune is usually best for keeping debug logic that you only want to look at in signaltap (even then, its best to send it to an output pin if you can)