how does quartus decide to remove logic?

In addition to Rysc's comment, I think, that your three above guesses why Quartus removes logic, are basically wrong. At least, if standard synthesis options are applied. E.g. driving a clock from a register may possibly cause timing problems, but creates a valid clock anyway. This clock and the logic driven by it would be removed only, if the register is stuck to a constant output, which may be the case in your design.