How do you connect to the DEV_CLRn pin when it is enabled

In Quartus > project > settings > assembler (or elsewhere), you get an option for DEV_CLR_n pin : "Active low device clear registers" OR "user I/O pin", opt for the first.

You don't have to code something : it is already connected to (asynchronous clear of) registers, I think.

Keep in mind that Quartus may add NOT gate push back, it depends of at which value do you clear your signals AND how Quartus synthesizes (have a look at warning messages).

May an other one be more expert on that.

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In Quartus > project > settings > assembler (or elsewhere), you get an option for DEV_CLR_n pin : "Active low device clear registers" OR "user I/O pin", opt for the first.

You don't have to code something : it is already connected to (asynchronous clear of) registers, I think.

Keep in mind that Quartus may add NOT gate push back, it depends of at which value do you clear your signals AND how Quartus synthesizes (have a look at warning messages).

May an other one be more expert on that.

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Yes, I have selected the first option and I understand that it will connect the external reset signal to all of the registers async clr. Now what I want to be able to do is to connect that global DEV_CLRn signal to some combinatorial logic in the device. How do I connect to that signal to the combinatorial logic? For example in Verilog:

assign signal1 = DEV_CLRn & signal2;

How do I get access to the DEV_CLRn signal to do this?

If you opt DEV_clr_n as reserved pin for clearing registers, that is what you did, you can NOT use it in your design as a user signal.

If you want to use this pin, set it as a "user I/O",

in your TOP LEVEL ports, add "DEV_CLRn" input (user input)

and in pin planner assign this user "DEV_CLRn" to "DEV_clr_n" pin (=B3 for Cyclone II).

ReThink your equation :

I don't know Verilog, but I guess

assign signal1 = DEV_CLRn & signal2;

is "signal1 receives DEV_CLRn AND signal2"

So if DEV_CLRn = '0' then signal 1 = '0'

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If you opt DEV_clr_n as reserved pin for clearing registers, that is what you did, you can NOT use it in your design as a user signal.

If you want to use this pin, set it as a "user I/O",

in your TOP LEVEL ports, add "DEV_CLRn" input (user input)

and in pin planner assign this user "DEV_CLRn" to "DEV_clr_n" pin (=B3 for Cyclone II).

ReThink your equation :

I don't know Verilog, but I guess

assign signal1 = DEV_CLRn & signal2;

is "signal1 receives DEV_CLRn AND signal2"

So if DEV_CLRn = '0' then signal 1 = '0'

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Yes, but if I make it user I/O, it will no longer do the asyn reset to all the flops in the part. I still want that plus I want to use the input for other things.

Sorry, I was not clear on my previous post. I will re-state.

Yes, but if I make it user I/O, it will no longer do the asyn reset to all the flops in the part. I still want that plus I want to use the reset signal on that input for things other than resetting all the flops, such as use in some combinatorial logic.