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In Quartus > project > settings > assembler (or elsewhere), you get an option for DEV_CLR_n pin : "Active low device clear registers" OR "user I/O pin", opt for the first.
You don't have to code something : it is already connected to (asynchronous clear of) registers, I think.
Keep in mind that Quartus may add NOT gate push back, it depends of at which value do you clear your signals AND how Quartus synthesizes (have a look at warning messages).
May an other one be more expert on that.
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Yes, I have selected the first option and I understand that it will connect the external reset signal to all of the registers async clr. Now what I want to be able to do is to connect that global DEV_CLRn signal to some combinatorial logic in the device. How do I connect to that signal to the combinatorial logic? For example in Verilog:
assign signal1 = DEV_CLRn & signal2;
How do I get access to the DEV_CLRn signal to do this?
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