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If you opt DEV_clr_n as reserved pin for clearing registers, that is what you did, you can NOT use it in your design as a user signal.
If you want to use this pin, set it as a "user I/O",
in your TOP LEVEL ports, add "DEV_CLRn" input (user input)
and in pin planner assign this user "DEV_CLRn" to "DEV_clr_n" pin (=B3 for Cyclone II).
ReThink your equation :
I don't know Verilog, but I guess
assign signal1 = DEV_CLRn & signal2;
is "signal1 receives DEV_CLRn AND signal2"
So if DEV_CLRn = '0' then signal 1 = '0'
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Yes, but if I make it user I/O, it will no longer do the asyn reset to all the flops in the part. I still want that plus I want to use the input for other things.
Honored Contributor
