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Altera_Forum
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11 years ago

How do you connect to the DEV_CLRn pin when it is enabled

I have enabled the device-wide reset (DEV_CLRn) to allow the input signal to reset all my registers. How do I connect to this global input so I can use it for other logic in my Verilog code?
Altera_Forum's avatar
Altera_Forum
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11 years ago

In Quartus > project > settings > assembler (or elsewhere), you get an option for DEV_CLR_n pin : "Active low device clear registers" OR "user I/O pin", opt for the first.

You don't have to code something : it is already connected to (asynchronous clear of) registers, I think.

Keep in mind that Quartus may add NOT gate push back, it depends of at which value do you clear your signals AND how Quartus synthesizes (have a look at warning messages).

May an other one be more expert on that.