Occasional Contributorhow do timing constraint for I2c bus
In my design, I used system clk = 3.125MHz to realize I2c SCL,SDA 200K i2c bus.
I used counter in the verilog, so both SCL and SDA are treated as data line.
Then, how to do timing contraint?
assign eeprom_scl = (eeprom_current_state == EEPROM_STATE_I2C_STAR && stsp_timer[7:0] < 8'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_STAR && stsp_timer[7:0] > 8'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_SLAW && data_timer[3:0] < 4'd4 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_SLAW && data_timer[3:0] < 4'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_SLAW && data_timer[3:0] > 4'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK0 && ackx_timer[7:0] < 8'd4 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK0 && ackx_timer[7:0] < 8'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_ACK0 && ackx_timer[7:0] > 8'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_REGR && data_timer[3:0] < 4'd4 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_REGR && data_timer[3:0] < 4'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_REGR && data_timer[3:0] > 4'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK1 && ackx_timer[7:0] < 8'd4 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK1 && ackx_timer[7:0] < 8'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_ACK1 && ackx_timer[7:0] > 8'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_DATW && data_timer[3:0] < 4'd4 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_DATW && data_timer[3:0] < 4'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_DATW && data_timer[3:0] > 4'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK2 && ackx_timer[7:0] < 8'd4 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK2 && ackx_timer[7:0] < 8'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_ACK2 && ackx_timer[7:0] > 8'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_STA2 && stsp_timer[7:0] < 8'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_STA2 && stsp_timer[7:0] > 8'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_SLAR && data_timer[3:0] < 4'd4 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_SLAR && data_timer[3:0] < 4'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_SLAR && data_timer[3:0] > 4'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK3 && ackx_timer[7:0] < 8'd4 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK3 && ackx_timer[7:0] < 8'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_ACK3 && ackx_timer[7:0] > 8'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_DATR && data_timer[3:0] < 4'd4 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_DATR && data_timer[3:0] < 4'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_DATR && data_timer[3:0] > 4'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK4 && ackx_timer[7:0] < 8'd4 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK4 && ackx_timer[7:0] < 8'd12)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_ACK4 && ackx_timer[7:0] > 8'd11)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_STOP && stsp_timer[7:0] < 8'd4 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_STOP && stsp_timer[7:0] > 8'd3 )? 1'bz : 1'bz;
assign eeprom_sda = (eeprom_current_state == EEPROM_STATE_I2C_STAR && stsp_timer[7:0] < 8'd8)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_STAR && stsp_timer[7:0] > 8'd7)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_SLAW && i2c_send[7] == 1'b1 )? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_SLAW && i2c_send[7] == 1'b0 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK0 )? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_REGR && i2c_send[7] == 1'b1 )? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_REGR && i2c_send[7] == 1'b0 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK1 )? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_DATW && i2c_send[7] == 1'b1 )? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_DATW && i2c_send[7] == 1'b0 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK2 )? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_STA2 && stsp_timer[7:0] < 8'd8)? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_STA2 && stsp_timer[7:0] > 8'd7)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_SLAR && i2c_send[7] == 1'b1 )? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_SLAR && i2c_send[7] == 1'b0 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK3 )? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_DATR && i2c_send[7] == 1'b1 )? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_DATR && i2c_send[7] == 1'b0 )? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_ACK4 )? 1'bz :
(eeprom_current_state == EEPROM_STATE_I2C_STOP && stsp_timer[7:0] < 8'd8)? 1'b0 :
(eeprom_current_state == EEPROM_STATE_I2C_STOP && stsp_timer[7:0] > 8'd7)? 1'bz : 1'bz;
Hello,
Sorry for the late response. You may use set_max_delay instead of set_input_delay since the I2C is pretty slow. You may use below constraint, this is the typical values used.
set_max_delay -from [get_ports {eeprom_scl}] 50
set_min_delay -from [get_ports {eeprom_scl}] 0
set_max_delay -from [get_ports {eeprom_sda}] 50
set_min_delay -from [get_ports {eeprom_sda}] 0
Regards,
Nurina
